1. Field of Invention
The present invention relates to a method for manufacturing a shallow trench isolation (STI) structure. More particularly, the present invention relates to a method for manufacturing an STI structure capable of forming a thicker liner oxide layer at the upper corner regions, thereby reducing the kink effect.
2. Description of Related Art
A device isolation region is a structure within the substrate for preventing the movement of carriers from one device to its neighbors. For example, device isolation regions are normally formed between metallic oxide semiconductor (MOS) transistors for reducing charge leakage. As the level of integration increases and line width of the device decreases to the sub-quarter micron (0.25 .mu.m) range, STI is one of the principle means for isolating devices. An STI structure is formed by first performing an anisotropic etching operation to etch out a trench in a semiconductor substrate, and then refilling the trench with insulating material.
FIGS. 1A through 1F are schematic, cross-sectional views showing the progression of manufacturing steps according to a conventional method of forming a shallow trench isolation structure.
First, as shown in FIG. 1A, a pad oxide layer 102 is formed over a silicon substrate 100. The pad oxide layer 102 is removed before the gate oxide layer is formed. Thereafter, a silicon nitride (Si.sub.3 N.sub.4) layer 104 is formed over the pad oxide layer 102 by performing a low-pressure chemical vapor deposition (LPCVD) operation.
Next, as shown in FIG. 1B, conventional method is used to form a patterned photoresist layer (not shown in the figure) over the silicon nitride layer 104. Then, using the patterned photoresist layer as a mask, the silicon nitride layer 104 is etched to form a silicon nitride layer 104a. Thereafter, using the silicon nitride layer 104a as a hard mask, the pad oxide layer 102 and the silicon substrate 100 are etched sequentially forming a pad oxide layer 102a and a trench 106 in the substrate 100. Hence, active regions 120 for laying the devices are patterned out. Finally, the photoresist layer is removed.
Next, as shown in FIG. 1C, a thermal oxidation method is used to form a liner layer 108 on the exposed surface inside the trench 106. The liner layer 108 extends all the way from the bottom of the trench 106 to the upper corner regions 130 and touch the pad oxide layer 102a. However, because the degree of oxidation at the upper corner regions 130 of the trench 106 is poor, thickness of the liner layer 108 in those regions 103 is thinner than the liner layer 108 in other places. In the subsequent step, silicon oxide material is deposited into the trench 106 by performing an atmospheric pressure chemical vapor deposition (APCVD) operation. The silicon oxide layer is then densified by heating to a high temperature, thereby forming an insulation layer 110.
Next, as shown in FIG. 1D, using the silicon nitride layer 104a as a polishing stop layer, a chemical-mechanical polishing (CMP) operation is carried out to remove a portion of the insulation layer 110. Finally, an insulation layer 110a is formed inside the trench 106.
Next, as shown in FIG. 1E, hot phosphoric acid (H.sub.3 PO.sub.4) solution is used to remove the silicon nitride layer 104a, and then hydrofluoric acid (HF) solution is used to remove the pad oxide layer 102a. Finally, an insulation layer 110b, also known as an STI region, is formed inside the substrate 100.
The pad oxide layer 102a is removed using hydrofluoric acid solution in a wet etching operation. Since wet etching is an isotropic etching operation, the surface of the insulation layer 110a next to the junction with the substrate 100 can be over-etched by hydrofluoric acid. Therefore, recess cavities 138 are likely to form in the junction area between the substrate 100 and the surface of the insulation layer 110b. These recess cavities 138 expose a portion of the thin pad oxide layer 102a at the upper corner regions 130 of the trench 106.
Next, as shown in FIG. 1F, a gate oxide layer 112 is grown over the substrate 100. The gate oxide layer 112 makes contact with a portion of the liner layer 108. Subsequently, when a gate terminal 114 is formed over the gate oxide layer 112, a corner parasitic MOS transistor will form in the thin liner layer 108 at the upper corner region 130 of the trench 106. Therefore, reliability of the gate terminal 114 at the upper corner region 130 of the trench 106 will be lower. Furthermore, when the device is in operation, accumulated electric charges at the upper corner regions 130 of the trench 106 will also lead to an increase in the electric field. Hence, the threshold voltage will be increased leading to the generation of abnormal subthreshold current, also known as the kink effect. Therefore, the conventional method of forming the STI structure lowers device quality and yield.
In light of the foregoing, there is a need to improve the method of forming STI structure.